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Preliminary Technical Data
FEATURES
Gain set with 1 external resistor Gain range: 1 to 1000 Input voltage goes to ground Input overdrive protection Very wide power supply range Dual supply: 1.3 V to 18 V Single supply: 2.6 V to 36 V Bandwidth (G = 1): 800 kHz CMRR (G = 1): 78 dB minimum Input noise: 22 nV/rt(Hz) Typical supply current: 350 A SOIC-8 and MSOP-8 packages
Wide Supply Range, Rail-to-Rail Output Instrumentation Amplifier AD8226
PIN CONFIGURATION
-IN RG RG +IN
1 2 3 4
AD8226
8 7 6
5
+VS VOUT REF -VS
07036-001
TOP VIEW (Not to Scale)
Figure 1.
APPLICATIONS
Industrial process controls Bridge amplifiers Medical instrumentation Portable data acquisition Multichannel systems
GENERAL DESCRIPTION
The AD8226 is a low cost instrumentation amplifier that requires only one external resistor to set any gain between 1 and 1000. The AD8226 is designed to work with a very wide range of voltages. It can operate on supplies ranging from 1.2 V to 18 V (2.4 V to 36 V single supply). The AD8226 comes with rail-to-rail output and a wide input range that includes the ability to go slightly below the negative supply. In addition, the AD8226 inputs can withstand voltages beyond the rail. The AD8226 is perfect for multichannel, space-constrained applications. Being a low power and low cost amplifier allows multiple channels to be used. The AD8226 has three grades. The A grade is the lower cost version and is specified for temperatures from -40C to +85C. The B grade is the higher performance version and is specified from -40C to +85C. The C grade version is the higher temperature version and is specified from -40C to +105C. All models are operational from -40C to +125C; behavior at these temperatures is shown in the typical performance curves. The AD8226 is available in MSOP and SOIC packages. Table 1. Instrumentation Amplifiers by Category
General Purpose AD82201 AD8221 AD8222 AD82241 AD8228
1
Zero Drift AD82311 AD8290 AD82931 AD85531 AD85561 AD85571
Military Grade AD620 AD621 AD524 AD526 AD624
Low Power AD6271 AD6231 AD82261
High Speed PGA AD8250 AD8251 AD8253
Rail-to-rail output.
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2008 Analog Devices, Inc. All rights reserved.
AD8226 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 Pin Configuration ............................................................................. 1 General Description ......................................................................... 1 Specifications..................................................................................... 3 Absolute Maximum Ratings ............................................................ 7 Thermal Resistance ...................................................................... 7 ESD Caution .................................................................................. 7 Pin Configuration and Function Descriptions ............................. 8 Theory of Operation ........................................................................ 9
Preliminary Technical Data
Architecture ...................................................................................9 Gain Selection ................................................................................9 Input Protection ............................................................................9 Reference Terminal .................................................................... 10 Input Voltage Range ................................................................... 10 Layout .......................................................................................... 10 Input Bias Current Return Path ............................................... 11 Radio Frequency Interference (RFI) ........................................ 11 Outline Dimensions ....................................................................... 12 Ordering Guide .......................................................................... 13
Rev. PrA | Page 2 of 16
Preliminary Technical Data SPECIFICATIONS
+VS = +15 V, -VS = -15 V, VREF = 0 V, TA = 25C, G = 1, RL = 10 k, unless otherwise noted. Table 2.
Parameter COMMON-MODE REJECTION RATIO (CMRR) CMRR DC to 60 Hz G=1 G = 10 G = 100 G = 1000 NOISE Voltage Noise, 1 kHz Input Voltage Noise, eNI Output Voltage Noise, eNO RTI G=1 G = 10 G = 100 to 1000 Current Noise VOLTAGE OFFSET Input Offset, VOSI Over Temperature Average temperature coefficient Output Offset, VOSO Over Temperature Average temperature coefficient Offset RTI vs. Supply (PSR) G=1 G = 10 G = 100 G = 1000 INPUT CURRENT Input Bias Current Over Temperature Average temperature coefficient Input Offset Current Over Temperature Average temperature coefficient REFERENCE INPUT RIN IIN Voltage Range Reference Gain to Output Reference Gain Error Conditions Min A, C Grade Typ Max Min B Grade Typ Max
AD8226
Unit
VCM = -10 V to +10 V 76 90 105 105 Total Noise: eN = eNI2 + (eNO/G2) VIN+, VIN-, VREF = 0 f = 0.1 Hz to 10 Hz 3 0.8 0.6 100 3 3 0.8 0.6 100 3 V p-p V p-p V p-p fA/Hz pA p-p 22 120 22 120 nV/Hz nV/Hz 86 100 105 105 dB dB dB dB
f = 1 kHz f = 0.1 Hz to 10 Hz Total offset voltage : VOS = VOSI + (VOSO/G) VS = 5 V to 15 V TA = TMIN to TMAX TA = TMIN to TMAX VS = 5 V to 15 V TA = TMIN to TMAX TA = TMIN to TMAX VS = 5 V to 15 V 80 100 105 105 10 5
500
200
V V V mV V/C dB dB dB dB
1500 2 15 90 105 105 105 20 100 3 5 5 100 7 -VS 1 0.01 +VS -VS 1 0.01 5 100 7 30 40 10 5 20 100 2
750 7
TA = TMIN to TMAX TA = TMIN to TMAX TA = TMIN to TMAX TA = TMIN to TMAX
30 40 2 5
nA nA pA/C nA nA pA/C k A V V/V %
+VS
Rev. PrA | Page 3 of 16
AD8226
Parameter DYNAMIC RESPONSE Small Signal -3 dB Bandwidth G=1 G = 10 G = 100 G =1000 Settling Time 0.01% G=1 G = 10 G = 100 G = 1000 Slew Rate GAIN Gain Range Gain Error G=1 G = 10 G = 100 G = 1000 Gain Nonlinearity G=1 G = 100 G = 1000 G = 1-100 Gain vs. Temperature G=1 G > 11 INPUT Input Impedance Differential Common Mode Input Operating Voltage Range2 Conditions Min A, C Grade Typ Max
Preliminary Technical Data
Min B Grade Typ Max Unit
1000 150 15 1.5 10 V step 22 22 50 600 0.5 1 1 VOUT 10 V 0.07 0.3 0.3 0.3 VOUT = -10 V to +10 V RL = 10 k RL = 10 k RL = 10 k RL = 2k TA = TMIN to TMAX TA = TMIN to TMAX VS = 1.35 V to 36 V 2 10 -50 1000 1
1000 150 15 1.5 22 22 50 600 0.5 1 1000 0.02 0.1 0.1 0.1
kHz kHz kHz kHz s s s s V/s V/s V/V % % % % ppm ppm ppm ppm
G=1 G = 5 to 100 G = 1 + (49.4k/RG)
2
5 -50
ppm/C ppm/C
2||2 2||2 TA = 25C TA = -40C TA = 105C TA = TMIN to TMAX VS = 1.35 V to 36 V RL = 10 k to ground TA = TMIN to TMAX RL = 100 k to ground TA = TMIN to TMAX -VS - 0.1 -VS - 0.15 -VS - 0.05 +VS -40 -VS + 0.2 -VS + 0.3 -VS + 0.1 -VS + 0.1 13 Dual supply operation TA = TMIN to TMAX A and B grades C grade -40 -40 -40 +85 +105 +125 -40 -40 1.3 350 18 400 1.3 +VS - 0.7 +VS - 0.9 +VS - 0.6 -VS +40 +VS - 0.2 +VS - 0.3 +VS - 0.1 +VS - 0.1 -VS - 0.1 -VS - 0.15 -VS - 0.05 +VS -40 -VS + 0.2 -VS + 0.3 -VS + 0.1 -VS + 0.1
2||2 2||2 +VS - 0.7 +VS - 0.9 +VS - 0.6 -VS +40 -VS + 0.2 +VS - 0.3 -VS + 0.1 -VS + 0.1 13 18 400
Input Overvoltage Range OUTPUT Output Swing Over Temperature Output Swing Over Temperature Short-Circuit Current POWER SUPPLY Operating Range Quiescent Current Over Temperature TEMPERATURE RANGE Specified Performance: TMIN to TMAX Operational
1 2
G||pF G||pF V V V V V V V V mA V A A C C
350
+85 +125
Does not include the effects of external resistor RG Input voltage range of the AD8226 input stage. Input range depends on common mode voltage, differential voltage, gain, and reference voltage. See the Input Voltage Range section in the Theory of Operation for more information.
Rev. PrA | Page 4 of 16
Preliminary Technical Data
+VS = 2.7 V, -VS = 0 V, VREF = 0 V, TA = 25C, G = 1, RL = 10 k, unless otherwise noted. Table 3.
Parameter COMMON-MODE REJECTION RATIO (CMRR) CMRR DC to 60 Hz G=1 G = 10 G = 100 G = 1000 NOISE Voltage Noise, 1 kHz Input Voltage Noise, eNI Output Voltage Noise, eNO RTI G=1 G = 10 G = 100 to 1000 Current Noise VOLTAGE OFFSET Input Offset, VOSI Over Temperature Average TC Output Offset, VOSO Over Temperature Average TC Offset RTI vs. Supply (PSR) G=1 G = 10 G = 100 G = 1000 INPUT CURRENT Input Bias Current Over Temperature Average TC Input Offset Current Over Temperature Average TC REFERENCE INPUT RIN IIN Voltage Range Reference Gain to Output Reference Gain Error DYNAMIC RESPONSE Small Signal -3 dB Bandwidth G=1 G = 10 G = 100 G =1000 Conditions Min A,C Grade Typ Max Min B Grade Typ Max
AD8226
Unit
VCM = 0 V to 1.7 V 76 90 105 105 Total Noise: eN = eNI2 + (eNO/G2) VIN+, VIN-, VREF= 0 f = 0.1 Hz to 10 Hz 3 0.8 0.6 100 3 3 0.8 0.6 100 3 V p-p V p-p V p-p fA/Hz pA p-p 22 120 22 120 nV/Hz nV/Hz 86 100 105 105 dB dB dB dB
f = 1 kHz f = 0.1 Hz to 10 Hz Total offset voltage : VOS = VOSI + (VOSO/G) VS = 0 V to 1.7 V TA = TMIN to TMAX TA = TMIN to TMAX VS = 0 V to 1.7 V TA = TMIN to TMAX TA = TMIN to TMAX VS = 0 V to 1.7 V 80 100 105 105 10 5
300 0.1 4 1200 15 90 105 105 105 20 100 3 5 5 100 7 -VS 1 0.01 +VS -VS 1 0.01 5 100 7 30 40 10 5 20 100 0.1
150 2 750 7
2
2
V V V/C V mV V/C dB dB dB dB
TA = TMIN to TMAX TA = TMIN to TMAX TA = TMIN to TMAX TA = TMIN to TMAX
30 40 2 5
nA nA pA/C nA nA pA/C k A V V/V %
+VS
1000 150 15 1.5
1000 150 15 1.5
kHz kHz kHz kHz
Rev. PrA | Page 5 of 16
AD8226
Parameter Settling Time 0.01% G=1 G=10 G = 100 G = 1000 Slew Rate GAIN Gain Range Gain Error G=1 G = 10 G = 100 G = 1000 Gain Nonlinearity G=1 G = 100 G = 1000 G = 1-100 Gain vs. Temperature G=1 G > 11 INPUT Input Impedance Differential Common Mode Input Operating Voltage Range2 Conditions 2 V step Min A,C Grade Typ Max 22 22 50 600 0.5 1 1 VOUT = 0 V to 1.7 V 0.07 0.3 0.3 0.3 VOUT = 0 V to 1.7 V RL = 10 k RL = 10 k RL = 10 k RL = 2 k TA = TMIN to TMAX TA = TMIN to TMAX -VS = 0V; +VS = 2.7 V to 36 V 2 10 -50 1000
Preliminary Technical Data
Min B Grade Typ Max 22 22 50 600 0.5 1 1 1000 0.02 0.1 0.1 0.1 Unit s s s s V/s V/s V/V % % % % ppm ppm ppm ppm 2 5 -50 ppm/C ppm/C
G=1 G = 5 to 100 G = 1 + (49.4 k/RG)
2||2 2||2 TA = 25C TA = -40C TA = 105C TA = TMIN to TMAX -VS = 0V; +VS = 2.7 V to 36 V RL = 10 k to opposite supply TA = TMIN to TMAX RL = 100 k to opposite supply TA = TMIN to TMAX - 0.1 - 0.15 - 0.05 +VS -40 0.2 0.3 0.1 0.1 13 Single supply operation TA = TMIN to TMAX A and B grades C grade -40 -40 -40 +85 +105 +125 -40 -40 2.6 300 350 36 2.6 +VS - 0.7 +VS - 0.9 +VS - 0.6 -VS +40 +VS - 0.2 +VS - 0.3 +VS - 0.1 +VS - 0.1 - 0.1 - 0.15 - 0.05 +VS -40 0.2 0.3 0.1 0.1
2||2 2||2 +VS - 0.7 +VS - 0.9 +VS - 0.6 -VS +40 -VS + 0.2 +VS - 0.3 -VS + 0.1 -VS + 0.1 13 36 350
G||pF G||pF V V V
Input Overvoltage Range OUTPUT Output Swing Over Temperature Output Swing Over Temperature Short-Circuit Current POWER SUPPLY Operating Range Quiescent Current Over Temperature TEMPERATURE RANGE Specified Performance: TMIN to TMAX Operational
1 2
V V V V mA V A A C C
300
+85 +125
Does not include the effects of external resistor RG Input voltage range of the AD8226 input stage. Input range depends on common mode voltage, differential voltage, gain, and reference voltage. See the Input Voltage Range section in the Theory of Operation for more information.
Rev. PrA | Page 6 of 16
Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter Supply Voltage Output Short-Circuit Current Maximum Voltage at -IN or +IN Minimum Voltage at -IN or +IN REF Voltage Differential Input Voltage Storage Temperature Range Operating Temperature Range1 Maximum Junction Temperature ESD Human Body Model Charge Device Model
1
AD8226
THERMAL RESISTANCE
Rating 18 V Indefinite -Vs + 40V +Vs - 40V Vs 40V -65C to +150C -40C to +125C 140C 2 kV 1 kV
JA is specified for a device in free air. Table 5.
Package 8-Lead MSOP, 4-Layer JEDEC Board 8-Lead SOIC, 4-Layer JEDEC Board JA 135 121 Unit C/W C/W
ESD CAUTION
Temperature range for specified performance is either -40C to +85C or -40C to +105C, depending on grade.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Rev. PrA | Page 7 of 16
AD8226 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
-IN RG RG +IN
1 2 3 4
Preliminary Technical Data
AD8226
8 7 6 5
+VS VOUT REF -VS
07036-002
TOP VIEW (Not to Scale)
Figure 2. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. 1 2, 3 4 5 6 7 8 Mnemonic -IN RG +IN -VS REF VOUT +VS Description Negative Input. Gain Setting Pins. Place gain resistor between these two pins. Positive Input. Negative Supply. Reference. Must be driven by low impedance. Output. Positive Supply.
Rev. PrA | Page 8 of 16
Preliminary Technical Data THEORY OF OPERATION
+VS NODE 3 RG +VS NODE 4 R3 50k R2 2.47k NODE 2 +VS Q1 NODE 1 +VS Q2 R5 50k -IN -VS
07036-003
AD8226
R1 -VS 2.47k
-VS
R4 50k A3 +VS R6 50k
+VS
OUT
-VS REF
+IN
A1
A2
-VS RB
UB
RB
-VS
GAIN STAGE
DIFFERENCE AMPLIFIER STAGE
Figure 3. Simplified Schematic
ARCHITECTURE
The AD8226 is based on the classic three op amp topology. This topology has two stages: a preamplifier to provide differential amplification, followed by a difference amplifier to remove the common-mode voltage. Figure 3 shows a simplified schematic of the AD8226. The first stage works as follows: in order to maintain a constant voltage across the Bias Resistor RB, Amplifier A1 must keep Node 3 a constant diode drop above the positive input voltage. Similarly, Amplifier A2 keeps Node 4 at a constant diode drop above the negative input voltage. Therefore a replica of the differential input voltage is placed across the gain setting resistor, RG. The current that flows across this resistance must also flow through the R1 and R2 resistors, creating a gained differential signal between the A2 and A1 outputs. Note that, in addition to a gained differential signal, the original commonmode signal, shifted a diode drop down, is also still present. The second stage is a difference amplifier, composed of A3 and four 50 k resistors. The purpose of this stage is to remove the common-mode signal from the amplified differential signal. Because the input amplifiers employ a current feedback architecture, the gain-bandwidth product of the AD8226 increases with gain, resulting in a system that does not suffer from the expected bandwidth loss of voltage feedback architectures at higher gains. The transfer function of the AD8226 is VOUT = G(VIN+ - VIN-) + VREF where
GAIN SELECTION
Placing a resistor across the RG terminals sets the gain of the AD8226, which can be calculated by referring to Table 7 or by using the following gain equation:
RG =
49.4 k G -1
Calculated Gain 1.990 4.984 9.998 19.93 50.40 100.0 199.4 495.0 991.0
Table 7. Gains Achieved Using 1% Resistors
1% Standard Table Value of RG () 49.9 k 12.4 k 5.49 k 2.61 k 1.00 k 499 249 100 49.9
The AD8226 defaults to G = 1 when no gain resistor is used. The tolerance and gain drift of the RG resistor should be added to the AD8226's specifications to determine the total gain accuracy of the system. When the gain resistor is not used, gain error and gain drift are minimal.
INPUT PROTECTION
The input terminals of the AD8226 have input protection that allows the input voltage to go beyond the rails without damaging the part. Maximum voltage is -Vs+40 V and minimum voltage is +Vs-40 V. For example: with 15 V supplies, the part can withstand input voltages of 25 V; with a 5 V single supply, maximum input voltage is 40 V and minimum input voltage is 35 V.
G =1+
49.4 k RG
Rev. PrA | Page 9 of 16
AD8226
REFERENCE TERMINAL
The output voltage of the AD8226 is developed with respect to the potential on the reference terminal. This is useful when the output signal needs to be offset to a precise midsupply level. For example, a voltage source can be tied to the REF pin to levelshift the output so that the AD8226 can drive a single-supply ADC. The REF pin is protected with ESD diodes and should not exceed either +VS or -VS by more than 0.3 V. For the best performance, source impedance to the REF terminal should be kept below 2 . As shown in Figure 3, the reference terminal, REF, is at one end of a 50 k resistor. Additional impedance at the REF terminal adds to this 50 k resistor and results in amplification of the signal connected to the positive input. The amplification from the additional RREF can be computed by 2(50 k + RREF)/100 k + RREF. Only the positive signal path is amplified; the negative path is unaffected. This uneven amplification degrades CMRR.
INCORRECT CORRECT
Preliminary Technical Data
(VDIFF )(GAIN ) + VCM + VREF 2 2 < + VS - 1.6 V
The common-mode input range shifts upwards with temperature. At cold temperatures, the part requires an extra 200 mV of headroom from the positive supply, and operation near the negative supply has more margin. Conversely, hot temperatures require less headroom from the positive supply, but are the worstcase conditions for input voltages near the negative supply.
LAYOUT
To ensure optimum performance of the AD8226 at the PCB level, care must be taken in the design of the board layout. The AD8226 pins are arranged in a logical manner to aid in this task.
-IN 1 RG 2 RG 3 +IN
4 8 7 6
+VS VOUT REF -VS
07036-005
AD8226
TOP VIEW (Not to Scale)
5
AD8226
REF V + V
AD8226
REF
Figure 5. Pinout Diagram
Common-Mode Rejection Ratio over Frequency
OP1177
-
07036-004
Figure 4. Driving the Reference Pin
INPUT VOLTAGE RANGE
The three op amp architecture of the AD8226 applies gain in the first stage before removing common-mode voltage in the difference amplifier stage. In addition, the input transistors in the first stage shift the common mode voltage up one diode drop (about 650 mV.) Therefore, internal nodes between the first and second stages (nodes 1 and 2 in Figure 3) experience a combination of gained signal, common-mode signal, and 650 mV. This combined signal can be limited by the voltage supplies even when the individual input and output signals are not. Figure XX through Figure XX show the allowable common-mode input voltage ranges for various output voltages and supply voltages. The following formulas can also be used to understand how the reference voltage (VREF), common mode input voltage (VCM), and differential input voltage (VDIFF) interact. These two formulas, along with the input range specifications in Table 1 and Table 3, set the boundaries where the part operates with best performance.
Poor layout can cause some of the common-mode signals to be converted to differential signals before reaching the in-amp. Such conversions occur when one input path has a frequency response that is different from the other. To keep CMRR across frequency high, input source impedance and capacitance of each path should be closely matched. Additional source resistance in the input path (for example, for input protection) should be placed close to the in-amp inputs, which minimizes their interaction with parasitic capacitance from the PCB traces. Parasitic capacitance at the gain setting pins can also affect CMRR over frequency. If the board design has a component at the gain setting pins (for example, a switch or jumper), the part should be chosen so that the parasitic capacitance is as small as possible.
Power Supplies
A stable dc voltage should be used to power the instrumentation amplifier. Noise on the supply pins can adversely affect performance. A 0.1 F capacitor should be placed as close as possible to each supply pin. As shown in Figure 6, a 10 F tantalum capacitor can be used farther away from the part. In most cases, it can be shared by other precision integrated circuits.
- V S - 0. 4 V <
(VDIFF )(GAIN ) + VCM < + VS - 0.9 V 2
Rev. PrA | Page 10 of 16
Preliminary Technical Data
+VS
AD8226
RADIO FREQUENCY INTERFERENCE (RFI)
RF rectification is often a problem when amplifiers are used in applications having strong RF signals. The disturbance can appear as a small dc offset voltage. High frequency signals can be filtered with a low-pass RC network placed at the input of the instrumentation amplifier, as shown in Figure 8. The filter limits the input signal bandwidth, according to the following relationship: FilterFrequencyDIFF =
07036-006
0.1F +IN
10F
AD8226
-IN REF
VOUT LOAD
1 2R(2CD + CC )
0.1F -VS
10F
FilterFrequencyCM = where CD 10 CC.
Figure 6. Supply Decoupling, REF, and Output Referred to Local Ground
1 2RCC
+VS 0.1F 10F
References
The output voltage of the AD8226 is developed with respect to the potential on the reference terminal. Care should be taken to tie REF to the appropriate local ground.
INPUT BIAS CURRENT RETURN PATH
The input bias current of the AD8226 must have a return path to ground. When the source, such as a thermocouple, cannot provide a return current path, one should be created, as shown in Figure 7.
INCORRECT
+VS
CC 1nF R 4.02k CD 10nF R 4.02k CC 1nF 0.1F -VS 10F
07036-008
+IN VOUT REF -IN
RG
AD8226
CORRECT
+VS
Figure 8. RFI Suppression
AD8226
REF
AD8226
REF
-VS TRANSFORMER +VS
-VS TRANSFORMER +VS
CD affects the difference signal, and CC affects the common-mode signal. Values of R and CC should be chosen to minimize RFI. Mismatch between the R x CC at the positive input and the R x CC at the negative input degrades the CMRR of the AD8226. By using a value of CD one magnitude larger than CC, the effect of the mismatch is reduced, and performance is improved.
AD8226
REF 10M -VS THERMOCOUPLE +VS C C
AD8226
REF
-VS THERMOCOUPLE
+VS
AD8226
C REF
1 fHIGH-PASS = 2RC C
R
AD8226
REF
R -VS CAPACITIVELY COUPLED -VS CAPACITIVELY COUPLED
07036-007
Figure 7. Creating an IBIAS Path
Rev. PrA | Page 11 of 16
AD8226 OUTLINE DIMENSIONS
3.20 3.00 2.80 5.15 4.90 4.65
Preliminary Technical Data
3.20 3.00 2.80
8
5
1
4
PIN 1 0.65 BSC 0.95 0.85 0.75 0.15 0.00 0.38 0.22 SEATING PLANE 1.10 MAX 8 0 0.80 0.60 0.40
0.23 0.08
COPLANARITY 0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 9. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters
5.00 (0.1968) 4.80 (0.1890)
8
5 4
4.00 (0.1574) 3.80 (0.1497)
1
6.20 (0.2441) 5.80 (0.2284)
1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY 0.10 SEATING PLANE
1.75 (0.0688) 1.35 (0.0532)
0.50 (0.0196) 0.25 (0.0099) 8 0 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157)
45
0.51 (0.0201) 0.31 (0.0122)
COMPLIANT TO JEDEC STANDARDS MS-012-A A CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 10. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches)
Rev. PrA | Page 12 of 16
012407-A
Preliminary Technical Data
ORDERING GUIDE
Model AD8226ARMZ1 AD8226ARMZ-RL1 AD8226ARMZ-R71 AD8226ARZ1 AD8226ARZ-RL1 AD8226ARZ-R71 AD8226BRMZ1 AD8226BRMZ-RL1 AD8226BRMZ-R71 AD8226BRZ1 AD8226BRZ-RL1 AD8226ARZ-R71 AD8226CRMZ1 AD8226CRMZ-RL1 AD8226CRMZ-R71 AD8226CRZ1 AD8226CRZ-RL1 AD8226CRZ-R71
1
AD8226
Package Description 8-Lead MSOP 8-Lead MSOP, 13" Tape and Reel 8-Lead MSOP, 7" Tape and Reel 8-Lead SOIC_N 8-Lead SOIC_N, 13" Tape and Reel 8-Lead SOIC_N, 7" Tape and Reel 8-Lead MSOP 8-Lead MSOP, 13" Tape and Reel 8-Lead MSOP, 7" Tape and Reel 8-Lead SOIC_N 8-Lead SOIC_N, 13" Tape and Reel 8-Lead SOIC_N, 7" Tape and Reel 8-Lead MSOP 8-Lead MSOP, 13" Tape and Reel 8-Lead MSOP, 7" Tape and Reel 8-Lead SOIC_N 8-Lead SOIC_N, 13" Tape and Reel 8-Lead SOIC_N, 7" Tape and Reel PackageOption RM-8 RM-8 RM-8 R-8 R-8 R-8 RM-8 RM-8 RM-8 R-8 R-8 R-8 RM-8 RM-8 RM-8 R-8 R-8 R-8 Branding Y16 Y16 Y16
Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C
Y1M Y1M Y1M
Y1Y Y1Y Y1Y
Z = RoHS Compliant Part.
Rev. PrA | Page 13 of 16
AD8226 NOTES
Preliminary Technical Data
Rev. PrA | Page 14 of 16
Preliminary Technical Data NOTES
AD8226
Rev. PrA | Page 15 of 16
AD8226 NOTES
Preliminary Technical Data
(c)2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR07036-0-10/08(PrA)
Rev. PrA | Page 16 of 16

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